Timing Simulator by Waveform Relaxation Considering the Feedback Effect

피이드백 효과를 고려한 파형이완 방식에 의한 Timing Simulator

  • Jun, Young Hyun (Dept. of Elec. Eng., KAIST) ;
  • Lee, Chang Woo (Dept. of Elec. Eng., KAIST) ;
  • Lee, Kijun (Dept. of Elec. Eng., Choong Nam Nat'l Univ.) ;
  • Park, Song Bai (Dept. of Elec. Eng., KAIST)
  • 전영현 (한국과학기술원 전기 및 전자공학과) ;
  • 이창우 (한국과학기술원 전기 및 전자공학과) ;
  • 이기준 (충남대학교 전자공학과) ;
  • 박송배 (한국과학기술원 전기 및 전자공학과)
  • Published : 1987.02.01

Abstract

Timing simulators are widely used nowadays for analyzing large-scale MOS digital circuits, which, however, have several limitations such as nonconvergence and/or in accuracy for circuits containing tightly coupled feedback elements or loops. This paper describes a new timing simulator which aims at solving these problems. The algorithm employed is based on the wave-form relaxation method, but exploits the signal flow along the feedback loops. Each of feedback loops is treated as one circuit block and then local iterations are performed to enhance the timing simulation. With these techniques, out simulator can analyze the MOS digital circuits with up to 5-20 times of the magnitude speed improvemnets as compared to SPICE2, while maintaining the accuracy.

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