대한전자공학회논문지 (Journal of the Korean Institute of Telematics and Electronics)
- 제22권5호
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- Pages.50-56
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- 1985
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- 1016-135X(pISSN)
CMOS Latch-Up 현상의 실험적 해석 및 그 방지책
Experimental Analysis and Suppression Method of CMOS Latch-Up Phenomena
- Go, Yo-Hwan (Dept. of Electrical Eng. and Electronic Eng., Korea advanced Institute of Science and Technology) ;
- Kim, Chung-Gi (Dept. of Electrical Eng. and Electronic Eng., Korea advanced Institute of Science and Technology) ;
- Gyeong, Jong-Min (Dept. of Electrical Eng. and Electronic Eng., Korea advanced Institute of Science and Technology)
- 발행 : 1985.09.01
초록
A common failure mechanism in bulk CMOS integrated circuits is the latch-up of parasitic SCR structure inherent in the bulk CMOS structure. Latch-up triggering and holding charac-teristics have been measured in the test devicrs which include conventional and Schottky-damped CMOS structures with various well depths and n+/p+ spacings. It is demonstrated that Schottky-clamped CMOS is more latch-up immune than conventional bulk CMOS. Finally, the simulation results by circuit simulation program (SPICE) are compared with measured results in order to verify the validity of the latch-up modal composed of nan, pnp transistors and two external resistors.
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