Proceedings of the Korean Institute of Information and Commucation Sciences Conference (한국정보통신학회:학술대회논문집)
- 2017.05a
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- Pages.691-693
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- 2017
Fast locking PLL with time difference detector
시간 차 감지기를 사용한 고속 위상고정루프
- Ko, Gi-Yeong (Pukyong National University) ;
- Choi, Hyuk-Hwan (Pukyong National University) ;
- Choi, Young-Shig (Pukyong National University)
- Published : 2017.05.31
Abstract
A novel structure of fast locking phase locked loop (PLL) with time difference detector and Lock status indicator (LSI) is proposed in this paper. Fast locking time is achieved using LSI. It has been simulated and proved by HSPICE in a CMOS
본 논문에서는 시간 차 감지기와 LSI(Lock Status Indicator)를 사용하여 빠른 위상고정 시간을 갖는 위상고정루프를 제안하였다. 제안된 위상고정루프는 1.8V