Tile Level Rate Control for High Efficiency Video Coding (HEVC) on Multi-core Platform

  • Published : 2015.11.06

Abstract

This paper proposes a tile level rate control for High Efficiency Video Coding (HEVC). The proposed tile level rate control is designed by considering the multi-core platform of tile in HEVC. The proposed tile level rate control allocates the number of bits for each tile based on the predetermined weight generated from the current picture level rate control. According to the experimental results, the proposed tile level rate control for HEVC on multi-core platform loses negligibly the bitrate accuracy about 0.07% on average over the reference software HM-14.0.

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