A 6.4-Gb/s/channel Asymmetric 4-PAM Transceiver for Memory Interface

An 6.4-Gb/s/channel 4-PAM transceiver is designed for a high speed memory application. The asymmetric 4-PAM signaling scheme is proposed to increase the voltage and time margins, and reduces the reference noise effect in a receiver by 33%. To reduce ISI in a channel, 1-tap pre-emphasis of a transmitter is used. The proposed asymmetric 4-PAM transceiver was implemented by using 0.13um 1-poly 6-metal CMOS process with 1.2V supply. The active area and power consumption of 1-charmel transceiver including a PLL are $0.294um^2$ and 6mW, respectively.

Hight speed memory application을 위하여 6.4-Gb/s/channel 4-PAM transceiver가 제안된다. Voltage margin과 time margin용 증가시키기 위하여 asymmetric 4-PAM scheme과 이를 위한 회로를 제안한다. 제안된 asymmetric 4-PAM scheme은 기존 회로에 비하여 송신단에서 33%의 기준전압 노이즈 영향을 줄인다. Channel의 ISI를 줄이기 위해서 transmitter의 1-tap pre-emphasis가 사용된다. 제안된 asymmetric 4-PAM transceiver는 1.2V supply 0.13um 1-poly 6-metal CMOS 공정에서 구현되었다. PLL을 포함한 1-channel transceiver의 면적과 전력소모는 각각 $0.294um^2$와 6mW이다.