Effect of cleaning process and surface morphology of silicon wafer for surface passivation enhancement of a-Si/c-Si heterojunction solar cells

실리콘 기판 습식 세정 및 표면 형상에 따른 a-Si:H/c-Si 이종접합 태양전지 패시배이션 특성

  • Published : 2010.06.17

Abstract

This paper investigates the dependence of a-Si:H/c-Si passivation and heterojunction solar cell performances on various cleaning processes of silicon wafer and surface morphology. It is observed that passivation quality of a-Si:H thin-films on c-Si wafer highly depends on wafer surface conditions. The MCLT(Minority carrier life time) of wafer incorporating intrinsic (i) a-Si:H as a passivation layer shows sensitive variation with cleaning process and surface morpholgy. By applying improved cleaning processes and surface morphology we can obtain the MCLT of $200{\mu}sec$ after H-termination and above 1.5msec after i a-Si:H thin film deposition, which has implied open circuit voltage of 0.720V.

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