한국전기전자재료학회:학술대회논문집 (Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference)

한국전기전자재료학회 (The Korean Institute of Electrical and Electronic Material Engineers)
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Engineered tunnel barrier를 갖는 SONOS 소자에서의 소거 속도 향상

Erasing characteristic improvement in SONOS type with engineered tunnel barrier

  • 발행 : 2009.06.18
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초록

Tunneling barrier engineered charge trap flash (TBE-CTF) memory capacitor were fabricated using the tunneling barrier engineering technique. Variable oxide thickness (VARIOT) barrier and CRESTED barrier consisting of thin $SiO_2$ and $Si_3N_4$ dielectrics layers were used as engineered tunneling barrier. The charge trapping characteristic with different metal gates are also investigated. A larger memory window was achieved from the TBE-CTF memory with high workfunction metal gate.

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