Effect of Scan-bias during Reset Period in a Negative Waveform

  • Park, W.H. (Dept. of Electronics and Electrical Eng., Dankook Univ.) ;
  • Lee, S.J. (Dept. of Electronics and Electrical Eng., Dankook Univ.) ;
  • Lee, J.Y. (Dept. of Electrical Eng., Myongji Univ.) ;
  • Kang, J. (Dept. of Electronics and Electrical Eng., Dankook Univ.)
  • 발행 : 2009.10.12

초록

A negative waveform having inverted polarity of conventional waveform during reset and sustain periods was proposed to improve the driving characteristics. In order to control the negative wall-charge distribution, a positive bias on the scan electrode was applied during reset period. Compared to 0 V scan-bias condition, at 8 V scan-bias the formative time lag was improved about 23.95 % and the average time lag was improved about 14.91 %. All experiments were performed with the 42-inch PDP module in XGA resolution.

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