Proceedings of the IEEK Conference (대한전자공학회:학술대회논문집)

The Institute of Electronics and Information Engineers (대한전자공학회)
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A Design on UWB LNA for Using $0.18{\mu}m$ CMOS

$0.18{\mu}m$ CMOS공정을 이용한UWB LNA

  • Hwang, In-Yong (Department of Electronics and Communications Engineering, Kwangwoon University) ;
  • Jung, Ha-Yong (Department of Electronics and Communications Engineering, Kwangwoon University) ;
  • Park, Chan-Hyeong (Department of Electronics and Communications Engineering, Kwangwoon University)
  • Published : 2008.06.18
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Abstract

In this paper, we proposed the design on LNA for $3{\sim}5\;GHz$ frequency with Using $0.18{\mu}m$CMOS technology. The LNA gain is 12-15 dB, and noise figure is lower than 5 dB and Input/output matching is lower than 10 dB in frequency range from 3 GHz to 5 GHz. The topology, which common source output of cascode is reduced noise figure and improved gain. Input common gate amplifier extend LNA's bandwidth.

본 논문에서는 CMOS $0.18\;{\mu}m$ 공정을 이용하여 UWB LNA를 설계하였다. UWB LNA $3{\sim}5GHz$의 대역 에서 전력이득은 12-15 dB, 잡음지수는 5 dB이하, 그리고 입력과 출력의 반사손실은 10 dB 이하의 특성을 보이도록 하였다. 캐스코드 구조를 이용하여 잡음을 억제하고 이득을 향상시켰으며, 입력매칭에 공통 게이트 증폭기를 이용하여 대역폭을 증가시켰다.

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