Proceedings of the IEEK Conference (대한전자공학회:학술대회논문집)
- 2008.06a
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- Pages.409-410
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- 2008
A design of synchronous nonlinear and parallel for pipeline stage on IP-based H.264 decoder implementation
IP기반 H.264 디코더 설계를 위한 동기식 비선형 및 병렬화 파이프라인 설계
- Ko, Byung-Soo (Dept. of Computer Engineering Kwangwoon University) ;
- Kong, Jin-Hyeung (Dept. of Computer Engineering Kwangwoon University)
- Published : 2008.06.18
Abstract
This paper presents nonlinear and parallel design for synchronous pipelining in IP-based H.264 decoder implementation. Since H.264 decoder includes the dataflow of feedback loop, the data dependency requires one NOP stage per pipelining latency to drop the throughput into 1/2. Further, it is found that, in execution time, the stage scheduled for MC is more occupied than that for CAVLD/ITQ/DF. The less efficient stage would be improved by nonlinear scheduling, while the fully-utilized stage could be accelerated by parallel scheduling of IP. The optimization yields 3 nonlinear {CAVLD&ITQ}|3 parallel (MC/IP&Rec.)| 3 nonlinear {DF} pipelined architecture for IP-based H.264 decoder. In experiments, the nonlinear and parallel pipelined H.264 decoder, including existing IPs, could deal with full HD video at 41.86MHz, in real time processing.
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