Hardware Design of SNR estimator for DVB-S2 terminal

DVB-S2 수신기를 위한 신호 대 잡음비 추정 하드웨어 설계

  • Park, Eun-Woo (Division of Electronics and Information Engineering, Chonbuk National University) ;
  • Yi, Jae-Ung (Division of Electronics and Information Engineering, Chonbuk National University) ;
  • Kim, Soo-Seong (Division of Electronics and Information Engineering, Chonbuk National University) ;
  • Im, Chae-Yong (Division of Electronics and Information Engineering, Chonbuk National University) ;
  • Yeo, Sung-Moon (Division of Electronics and Information Engineering, Chonbuk National University) ;
  • Kim, Soo-Young (Division of Electronics and Information Engineering, Chonbuk National University)
  • 박은우 (전북대학교 전자정보 공학부) ;
  • 이재웅 (전북대학교 전자정보 공학부) ;
  • 김수성 (전북대학교 전자정보 공학부) ;
  • 임채용 (전북대학교 전자정보 공학부) ;
  • 여성문 (전북대학교 전자정보 공학부) ;
  • 김수영 (전북대학교 전자정보 공학부)
  • Published : 2007.07.11

Abstract

This paper presents an efficient and simple hardware design of signal to noise ratio (SNR) estimator for DVB-S2 system. The estimator investigates the distribution of the received symbols by simply using two comparators and a counter, and calculates the address of an LUT where the corresponding SNR value is located. In this paper, we demonstrate the functional and timing simulation results of the FPGA implementation of proposed structure.

Keywords