전력전자학회:학술대회논문집 (Proceedings of the KIPE Conference)
- 전력전자학회 2007년도 추계학술대회 논문집
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- Pages.215-217
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- 2007
AC PDP에서 고속 어드레싱을 위한 네거티브 리셋 파형 및 구동회로의 구현
Implementation of the Negative Reset Waveform and Driving Circuit for High Speed Addressing in AC PDP
- Lim, Hyun-Muk (Dept. of Electronics Eng., Dankook University) ;
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Lim, Seung-Beom
(Dept. of Electrical Eng., Dankook University) ;
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Lee, Jun-Young
(Dept. of Electronics Eng., Dankook University) ;
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Kang, Jung-Won
(Dept. of Electronics Eng., Dankook University) ;
- Hong, Soon-Chan (Dept. of Electrical Eng., Dankook University)
- 발행 : 2007.11.30
초록
Recently, the demand for high definition TV is being increased by beginning of the digital broadcasting. The higher resolution of PDP is, the longer addressing time become, then, the sustain period for display image decreases. Because of the reason, dual-scan method which synchronously write information of an image on top and bottom of the screen is used for the high definition PDP. However, as the price competition of PDP becomes severe, we can`t avoid turning to a single-scan method which uses only a half of an expensive address IC. Accordingly, the sustain period becomes much shorter than prior method. In case of XGA level, it is impossible to display, eventually. In this paper, we are going to prove usefulness by realizing negative reset waveform and the driving circuit for high speed addressing.
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