대한전기학회:학술대회논문집 (Proceedings of the KIEE Conference)

대한전기학회 (The Korean Institute of Electrical Engineers)
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10Gbps CMOS 클록/데이터 복원회로 설계

Design of a 10Gbps CMOS Clock and Data Recovery Circuit

  • Cha, C.H. (Dept. of Electronic Engineering University of Incheon) ;
  • Shim, H.C. (Dept. of Electronic Engineering University of Incheon) ;
  • Jeon, S.H. (Dept. of Electronic Engineering University of Incheon) ;
  • Yu, C.G. (Dept. of Electronic Engineering University of Incheon)
  • 발행 : 2007.10.26
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초록

In this paper, a 10Gbps Clock and Data Recovery circuit is designed in $0.18{\mu}m$ CMOS Technology. The circuit incorporates a multiphase LC oscillator, a quarter-rate Bang-Bang phase detector, a Charge Pump and a second order loop filter. The simulation results show that the designed circuit has a peak-to-peak clock jitter of 4.1ps and a peak-to-peak recovered data jitter of 8ps while consuming about 44mW from a 1.8V supply.

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