대한전자공학회:학술대회논문집 (Proceedings of the IEEK Conference)
- 대한전자공학회 2006년도 하계종합학술대회
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- Pages.965-966
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- 2006
Automatic Generation of Transaction Level Code for Fast SoC Design Space Exploration
- Lee, Gang-Hee (Design Automation Lab., Seoul National Univ) ;
- Ahn, Yong-Jin (Design Automation Lab., Seoul National Univ) ;
- Choi, Ki-Young (Design Automation Lab., Seoul National Univ)
- 발행 : 2006.06.21
초록
As billion transistors system-on-chip (SoC) design becomes a reality, the productivity gap between rapidly increasing design complexity and designer productivity lagging behind is becoming a more serious problem to be solved. To reduce the gap, we present a system that generates executable transaction level models automatically. It speed up the SoC design space exploration process at various abstraction levels.
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