Proceedings of the IEEK Conference (대한전자공학회:학술대회논문집)

The Institute of Electronics and Information Engineers (대한전자공학회)
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A Row Decoder Design and Simulation Considering The Characteristics of PoRAM

PoRAM의 특성을 고려한 행 디코더 설계 및 시뮬레이션

  • Park, Yu-Jin (Div. Electrical and computer Engineering Hanyang University) ;
  • Kim, Jung-Ha (Div. Electrical and computer Engineering Hanyang University) ;
  • Cho, Ja-Young (Div. Electrical and computer Engineering Hanyang University) ;
  • Lee, Sang-Sun (Div. Electrical and computer Engineering Hanyang University)
  • 박유진 (한양대학교 공과대학 전자전기컴퓨터공학부) ;
  • 김정하 (한양대학교 공과대학 전자전기컴퓨터공학부) ;
  • 조자영 (한양대학교 공과대학 전자전기컴퓨터공학부) ;
  • 이상선 (한양대학교 공과대학 전자전기컴퓨터공학부)
  • Published : 2006.06.21
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Abstract

The low crosstalk row-decoder is studied for PoRAM applications. Because polymer-based memories can be more densely integrated than established silicon-based ones, PoRAM is highly sensitive for the crosstalk problem. To overcome the problem and to suggest the suitable decoder for PoRAM, this paper shows the comparison of the row-path characteristics for both the 2-stage dynamic logic decoder and the 2-stage static logic decoder. Moreover, to suppress the Glitch effect which is observed by using the static logic decoder, the Master-Slave(M/S) D-Flip/Flop(D-F/F) is applied as a deglitch. Finally, the improved output result of the 2-stage static logic decoder with the M/S D-F/F is shown..

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