대한전자공학회:학술대회논문집 (Proceedings of the IEEK Conference)

대한전자공학회 (The Institute of Electronics and Information Engineers)
권호 표지

MB-OFDM UWB System용 Fast Setting PLL 개발

Development of the fast setting PLL for MB-OFDM UWB system

  • 이영재 (한국전자통신연구원 IT 융합부품연구소 SoC 연구개발 그룹) ;
  • 현석봉 (한국전자통신연구원 IT 융합부품연구소 SoC 연구개발 그룹) ;
  • 탁금영 (LG 전자 기술원) ;
  • 김천수 (한국전자통신연구원 IT 융합부품연구소 SoC 연구개발 그룹) ;
  • 유현규 (한국전자통신연구원 IT 융합부품연구소 SoC 연구개발 그룹)
  • Lee, Young-Jae (IT Conversion and Components Laboratory, SoC R&D Group Electronics and Telecommunications Research Institute) ;
  • Hyun, Seok-Bong (IT Conversion and Components Laboratory, SoC R&D Group Electronics and Telecommunications Research Institute) ;
  • Tak, Geum-Young ;
  • Kim, Cheon-Soo (IT Conversion and Components Laboratory, SoC R&D Group Electronics and Telecommunications Research Institute) ;
  • Yu, Hyun-Kyu (IT Conversion and Components Laboratory, SoC R&D Group Electronics and Telecommunications Research Institute)
  • 발행 : 2006.06.21
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초록

A CMOS phase-locked loop (PLL) which synthesizes frequencies between $6.336{\sim}8.976GHz$ in steps of 528MHz and settles in approximately 150ns using the 528MHz reference clock is presented. Frequency hopping between the bands in the each mode is critical point to design the PLL in multi-band orthogonal frequency division multiplexing (OFDM) because frequency switching between each band is less than 9.5ns. To achieve the fast loop settling, integer-N PLL that operates with the high reference frequency to meet the settling requirement is implemented. Two PLLs that operate at 9GHz and 528MHz is integrated and shows the band hopping lower than 1ns.

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