Proceedings of the IEEK Conference (대한전자공학회:학술대회논문집)
- 2006.06a
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- Pages.589-590
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- 2006
A Study on the novel Nano ESD Protection Circuit with High Speed and Low Voltage
새로운 구조의 나노소자기반 고속/저전압 ESD 보호회로에 대한 연구
- Lee, Jo-Woon (Department of Electronic engineering Seokyeong University) ;
- Yuk, Seung-Bum (Department of Electronic engineering Seokyeong University) ;
- Koo, Yong-Seo (Electronics and Telecommunications Research Institute) ;
- Kim, Kui-Dong (Electronics and Telecommunications Research Institute) ;
- Kwon, Jong-Ki (Department of Electronic engineering Seokyeong University)
- Published : 2006.06.21
Abstract
A novel Triple-Well P-type Triggered Silicon Controlled Rectifier (TWPTSCR) for on-chip ESD protection implemented with a triple-well CMOS technology is presented. Unlike conventional SCR devices, the proposed TWPTSCR offers a reduced triggering voltage level as well as the enhanced ESD performance of the SCR devices. From the experimental results, the TWPTSCR with a device width of 20um has the triggering voltage of 1.1V.
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