대한전자공학회:학술대회논문집 (Proceedings of the IEEK Conference)
- 대한전자공학회 2006년도 하계종합학술대회
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- Pages.581-582
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- 2006
게이트 레이아웃을 이용한 70nm nMOSFET 초고주파 성능 최적화
Optimization of 70nm nMOSFET Performance using gate layout
- 홍승호 (포항공과대학교 전자전기공학과) ;
- 박민상 (포항공과대학교 전자전기공학과) ;
- 정성우 (포항공과대학교 전자전기공학과) ;
- 강희성 (삼성전자 System LSI 사업부) ;
- 정윤하 (포항공과대학교 전자전기공학과)
- Hong, Seung-Ho (Department of Electronic and Electrical Engineering Pohang University of Science and Technology) ;
- Park, Min-Sang (Department of Electronic and Electrical Engineering Pohang University of Science and Technology) ;
- Jung, Sung-Woo (Department of Electronic and Electrical Engineering Pohang University of Science and Technology) ;
- Kang, Hee-Sung (System LSI Division, Samsung Electronics Co., Ltd.) ;
- Jeong, Yoon-Ha (Department of Electronic and Electrical Engineering Pohang University of Science and Technology)
- 발행 : 2006.06.21
초록
In this paper, we investigate three different types of multi-fingered layout nMOSFET devices with varying
키워드