대한전자공학회:학술대회논문집 (Proceedings of the IEEK Conference)

대한전자공학회 (The Institute of Electronics and Information Engineers)
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빠른 스위칭 시간과 저 위상잡음 특성을 가지는 PHS용 주파수 합성기의 설계

A design of fast switching time, low phase noise PHS frequency synthesizer

  • 정성규 (건국대학교 정보통신대학 전자공학부) ;
  • 정지훈 (건국대학교 정보통신대학 전자공학부) ;
  • 부영건 (건국대학교 정보통신대학 전자공학부) ;
  • 김진경 (건국대학교 정보통신대학 전자공학부) ;
  • 장석환 (건국대학교 정보통신대학 전자공학부) ;
  • 이강윤 (건국대학교 정보통신대학 전자공학부)
  • Jung, Sung-Kyu (Department of Electronic Engineering Konkuk University) ;
  • Jung, Ji-Hoon (Department of Electronic Engineering Konkuk University) ;
  • Pu, Young-Gun (Department of Electronic Engineering Konkuk University) ;
  • Kim, Jin-Kyung (Department of Electronic Engineering Konkuk University) ;
  • Jang, Suk-Hwan (Department of Electronic Engineering Konkuk University) ;
  • Lee, Kang-Yoon (Department of Electronic Engineering Konkuk University)
  • 발행 : 2006.06.21
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초록

This paper presents a fast switching CMOS frequency synthesizer with a new coarse tuning method for PHS applications. To achieve the fast lock-time and the low phase noise performance, an efficient bandwidth control scheme is proposed. Charge pump up/down current mismatches are compensated with the current mismatch compensation block. Also, the proposed coarse tuning method selects the optimal tuning capacitances of the LC-VCO to optimize the phase noise and the lock-time. The measured lock-time is about $20{\mu}s$. This chip is fabricated with $0.25{\mu}m$ CMOS technology, and the die area is $0.7mm{\times}2.1mm$. The power consumption is 54mW at 2.7V supply voltage.

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