Bias stress effect in organic thin-film transistors with cross-linked PVA gate dielectric and its reduction method using $SiO_2$ blocking layer

  • Park, Dong-Wook (Inter-University Semiconductor Research Center (ISRC) and School of Electrical Engineering, Seoul National University) ;
  • Lee, Cheon-An (Inter-University Semiconductor Research Center (ISRC) and School of Electrical Engineering, Seoul National University) ;
  • Jung, Keum-Dong (Inter-University Semiconductor Research Center (ISRC) and School of Electrical Engineering, Seoul National University)
  • Published : 2006.08.22

Abstract

Bias stress effect in pentacene organic thin-flim transistors with cross-linked PVA gate dielectric is analyzed. For negative gate bias stress, positive threshold voltage shift is observed. The injected charges from the gate electrode to the defect states of gate dielectric are regarded as the main origin of $V_T$ shift. The reduced bias stress effect using $SiO_2$ blocking layer confirms the assumed mechanism. It is also demonstrated that the inverter with $SiO_2$ blocking layer shows the negligible hysteresis owing to the reduced bias stress effect.

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