Proceedings of the KIEE Conference (대한전기학회:학술대회논문집)

The Korean Institute of Electrical Engineers (대한전기학회)
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Process Characteristics by Pattern Size in CMP Process of BLT Films

BLT박막의 화학적기계적연마 공정시 패턴 크기에 따른 공정 특성

  • Shin, Sang-Hun (Department of Electrical Engineering, Chosun University) ;
  • Lee, Woo-Sun (Department of Electrical Engineering, Chosun University)
  • 신상헌 (조선대학교 전기공학과) ;
  • 이우선 (조선대학교 전기공학과)
  • Published : 2006.10.27
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Abstract

In this work, we first applied the chemical mechanical polishing (CMP) process to the planarization of ferroelectric film in order to obtain a good planarity of electrode/ferroelectric film interface. $Bi_{3.25}La_{0.75}Ti_{3}O_{12}$ (BLT) ferroelectric film was fabricated by the sol-gel method. However, there have been serious problems in CMP in terms of repeatability and defects in patterned wafer. Especially, dishing & erosion defects increase the resistance because they decrease the interconnect section area, and ultimately reduce the lifetime of the semiconductor. Cross-sections of the wafer before and after CMP were examined by Scanning electron microscope(SEM). Process characteristics of non-dishing and erosion were investigated.

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