대한전자공학회:학술대회논문집 (Proceedings of the IEEK Conference)
- 대한전자공학회 2005년도 추계종합학술대회
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- Pages.865-868
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- 2005
클록 게이팅을 이용한 저전력 UART 설계
A Low Power UART Design by Using Clock-gating
- Oh, Tae-Young (Department of Electronic Engineering, Chongju University) ;
- Song, Sung-Wan (Department of Electronic Engineering, Chongju University) ;
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Kim, Hi-Seok
(Department of Electronic Engineering, Chongju University)
- 발행 : 2005.11.26
초록
This paper presents a Clock-gating technique that reduces power dissipation of the sequential circuits in the system. The Master Clock of a Clock-gating technique is formed by a quaternary variable. It uses the covering relationship between the triggering transition of the clock and the active cycles of various flip-flops to generate a slave clock for each flip-flop in the circuit. At current RTL designs flip-flop is acted by Master clock's triggering but the Slave Clock of Clock-gating technique doesn't occur trigger when external input conditions have not matched with a condition of logic table. We have applied our clocking technique to UART controller of 8bit microprocess
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