대한전자공학회:학술대회논문집 (Proceedings of the IEEK Conference)
- 대한전자공학회 2005년도 추계종합학술대회
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- Pages.699-702
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- 2005
Redundant Multi-Valued Logic을 이용한 4.5Gb/s CMOS 디멀티플렉서 구현
Implementation of 4.5Gb/s CMOS Demultiplexer Using Redundant Multi-Valued Logic
- Kim, Tae-Sang (Department of Electrical and Computer Engineering, Kangwon National University) ;
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Kim, Jeong-Beom
(Department of Electrical and Computer Engineering, Kangwon National University)
- 발행 : 2005.11.26
초록
This paper describes a high speed interface using redundant multi-valued logic for high speed communication ICs. This circuit is composed of encoding circuit and decoding circuit. Because of the multi-valued data conversion, this circuit makes it possible to achieve higher operating speeds than that of a conventional binary logic. Using this logic, a 1:4 DEMUX (demultiplexer) was designed using a 0.35um standard CMOS technology. Proposed circuit is achieved an operating speed of 4.5Gb/s with a supply voltage of 3.3V and with power consumption of 53mW.
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