Proceedings of the KIEE Conference (대한전기학회:학술대회논문집)
- 2005.07d
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- Pages.3058-3060
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- 2005
Design of a Analog Multiplier for low-voltage low-power
저전압 저전력 아날로그 멀티플라이어 설계
- Lee, Goun-Ho (Information Technology & Engineering Jeonju University) ;
- Seul, Nam-O (Seonam University Electrical & Electric Dept.)
- Published : 2005.07.18
Abstract
In this paper, the CMOS four-quadrant analog multipliers for low-voltage low-power applications are presented. The circuit approach is based on the characteristic of the LV (Low-Voltage) composite transistor which is one of the useful analog building blocks. SPICE simulations are carried out to examine the performances of the designed multipliers. Simulation results are obtained by
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