대한전자공학회:학술대회논문집 (Proceedings of the IEEK Conference)
- 대한전자공학회 2004년도 학술대회지
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- Pages.455-459
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- 2004
A Study on the Optimization of the Layout for the ESD Protection Circuit in O.18um CMOS Silicide Process
- Lim Ho Jeong (Dept of Electronic Engineering, HanYang University) ;
- Park Jae Eun (Dept of Electronic Engineering, HanYang University) ;
- Kim Tae Hwan (Dept of Electronic Engineering, HanYang University) ;
- Kwack Kae Dal (Dept of Electronic Engineering, HanYang University)
- 발행 : 2004.08.01
초록
Electrostatic discharge(ESD) is a serious reliability concern. It causes approximately most of all field failures of integrated circuits. Inevitably, future IC technologies will shrink the dimensions of interconnects, gate oxides, and junction depths, causing ICs to be increasingly susceptible to ESD-induced damage [1][2][3]. This thesis shows the optimization of the ESD protection circuit based on the tested results of MM (Machine Model) and HBM (Human Body Model), regardless of existing Reference in fully silicided 0.18 um CMOS process. His thesis found that, by the formation of silicide in a source and drain contact, the dimensions around the contact had a less influence on the ESD robustness and the channel width had a large influence on the ESD robustness [8].
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