Proceedings of the Korean Information Science Society Conference (한국정보과학회:학술대회논문집)
- 2004.04a
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- Pages.931-933
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- 2004
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- 1598-5164(pISSN)
Fine-Grain Pipeline Control Circuit for High Performance Microprocessors
고성능 마이크로프로세서를 위한 파이프라인 제어로직
Abstract
In a SoC environment, asynchronous design techniques offer solutions for problems of synchronous design techniques. Asynchronous FIFOs have the advantages of easier interconnection methods and higher throughput than synchronous ones. Low latency and high throughput are two imp ortant standards in asynchronous FIFOs. We present low latency asynchronous FIFO in the paper, which optimizes GasP[6]. Pre-layout of HSPICE simulations of a 8-stage FIFO on 1-bit datapath using Anam's 0.25
Keywords