Proceedings of the IEEK Conference (대한전자공학회:학술대회논문집)

The Institute of Electronics and Information Engineers (대한전자공학회)
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A Multi-Level HW/SW Partitioning Algorithm for SoCs

SoC를 위한 다단 HW/SW 분할 알고리듬

  • Ahn, Byung-Gyu (Dept. of Information & Communications, Hanyang University) ;
  • Sihn, Bong-Sik (Dept. of Information & Communications, Hanyang University) ;
  • Chong, Jong-Wha (Dept. of Information & Communications, Hanyang University)
  • 안병규 (한양대학교 정보통신대학원) ;
  • 신봉식 (한양대학교 정보통신대학원) ;
  • 정정화 (한양대학교 정보통신대학원)
  • Published : 2004.06.01
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Abstract

In this paper, we present a new efficient multi-level hardware/software partitioning algorithm for system-on-a-chip design. Originally the multi-level partitioning algorithm are proposed to enhance the performance of previous iterative improvement partitioning algorithm for large scale circuits. But when designing very complex and heterogeneous SoCs, the HW/SW partitioning decision needs to be made prior to refining the system description. In this paper, we present a new method, based on multi-level algorithm, which can cover SoC design. The different variants of algorithm are evaluated by a randomly generated test graph. The experimental results on test graphs show improvement average $9.85\%$ and $8.51\%$ in total communication costs over FM and CLIP respectively.

Keywords