대한전자공학회:학술대회논문집 (Proceedings of the IEEK Conference)
- 대한전자공학회 2004년도 하계종합학술대회 논문집(2)
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- Pages.545-548
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- 2004
고속, 고해상도 CMOS 샘플 앤 홀드 회로
High Speed, High Resolution CMOS Sample and Hold Circuit
- Kim Won-Youn (Dept. of Electronic Engineering, Inha University) ;
- Park Kong-Soon (Silicon Works(Inc)) ;
- Park Sang-Wook (Dept. of Electronic Engineering, Inha University) ;
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Yoon Kwang-Sub
(Dept. of Electronic Engineering, Inha University)
- 발행 : 2004.06.01
초록
The paper describes the design of high-speed, high-resolution Sample-and-Hold circuit which shows the conversion rate 80MHz and the power supply of 3.3v with 0.35um CMOS 2-poly 4-metal process for high-speed, high resolution Analog-to-Digital Converter. For improving Dynamic performance of Sample-and-Hold, Two Double bootstrap switch and high performance operational amplifier with gain booster, which are used. and For physical stability of Sample and Hold circuit, reduces excess voltage of gate in bootstrap switch. Simulation results using HSPICE shows the SFDR of 71dB, 75dB in conversion rate of 80MHz result for two inputs(0.5Vpp, 10MHz and 1Vpp, 10MHz) and the power dissipation of 48mW at single 3.3V supply voltage.
키워드