대한전자공학회:학술대회논문집 (Proceedings of the IEEK Conference)
- 대한전자공학회 2004년도 하계종합학술대회 논문집(2)
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- Pages.533-536
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- 2004
10-bit 32Msps A/D 변환기의 설계
Design of the 10-bit 32Msps Analog to Digital Converter
- Kim Pan-Jong (Dongguk University Department of Semiconductor Science) ;
- Song Min-Kyu (Dongguk University Department of Semiconductor Science)
- 발행 : 2004.06.01
초록
In this paper, CMOS A/D converter with 10bit 32MSPS at 3.3V is designed for HPNA 2.0. In order to obtain the resolution of 10bit and the character of high-speed operation, we present multi-stage type architecture. That consist of sample and hold(S&H), 4bit flash ADC and 4bit Multiplier D/A Converter (MADC) also the Overflow and Underflow for timing error correct of Digital Correct ion Logic (DCL). The proposed ADC is based on 0.35um 3-poly 5-metal N-well CMOS technology. and it consumes 130mW at 3.3V power supply.
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