A Design of Planner Linear Group Delay Equalizer

평면형 군위상 지연 선형화기의 설계

  • Kwonn, Hyuk-Moon (Dept. of Electrical and Computer Eng. Kangwon National University) ;
  • Choi, Won-Kyu (Dept. of Electrical and Computer Eng. Kangwon National University) ;
  • Hwang, Hee-Yong (Dept. of Electrical and Computer Eng. Kangwon National University) ;
  • Choi, Kyung (Dept. of Electrical and Computer Eng. Kangwon National University)
  • 권혁문 (강원대학교 전기전자정보통신공학부) ;
  • 최원규 (강원대학교 전기전자정보통신공학부) ;
  • 황희용 (강원대학교 전기전자정보통신공학부) ;
  • 최경 (강원대학교 전기전자정보통신공학부)
  • Published : 2003.11.15

Abstract

In This paper, a pole-zero optimized design method for multi-layed planar interdigital stripeline linear group delay bandpass filter with tap input port is presented. As a design example, a four-pole group delay filter with center frequency of 2.14GHz, bandwidth of 160MHz, and group delay variation of ${\pm}0.1nS$ for LTCC technology or multilayerd PCB technology is designed. In the design process, as well the whole structure is not necessary to be simulated, and within three times of optimizing process we have good result as well. This design method could be useful for controlling error correction of manufacturing process as well as design stage.

Keywords