An Efficient Hardware Architecture of Intra Prediction in H.264/AVC Decoder

H.264/AVC 디코더용 인트라 예측기의 효율적인 하드웨어 구현

H.264/AVC is the upcoming video coding standard of ITU-T H.264 and ISO MPEG-4 AVC. The new standard can achieve a significant improvement up to 50％ in compression ratio compared to MPEG-4 advanced simple profile. In this paper, we propose the novel intra prediction scheme to speed up intra prediction process in H.264/AVC decoder and show the hardware architecture for it. The proposed scheme uses the concurrent processing of the 4$\times$4 intra prediction, which is based on that some 4$\times$4 block pairs in a 16$\times$16 luma block can be processed concurrently. The proposed scheme can reduce intra prediction time by 33 ％.