Proceedings of the IEEK Conference (대한전자공학회:학술대회논문집)
- 2003.07b
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- Pages.1229-1232
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- 2003
Design of Pipeline Analog-to-Digital Converter Using a Parallel S/H
병렬 S/H를 이용한 파이프라인 ADC설계
Abstract
In this paper, The High-speed Low-power Analog-to-Digital Convener Archecture is proposed using the parallel S/H for High-speed operation. This technique can significantly reduce the sampling frequency per S/H channel. The Analog-to-Digital Converter is designed using 0.35
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