10bit 50MS/s CMOS Pipeline Analog-Digital Converter

10bit 50MS/s CMOS 파이프라인 아날로그-디지털 변환기

  • 김대용 (고려대학교 전자공학과 ASIC 설계 연구실) ;
  • 김길수 (고려대학교 전자공학과 ASIC 설계 연구실) ;
  • 김수원 (고려대학교 전자공학과 ASIC 설계 연구실)
  • Published : 2003.07.01

Abstract

This paper presents A/D converter for the signal processing of infrared sensor and CMOS image sensor. The A/D converter designed in a 0.25um CMOS process provides a resolution of 10bits at a sampling rate of 50MS/s while dissipating 67mW at 2.5V supply voltage. This A/D converter is based on a pipeline architecture in which the number of bits converted per stage and the stage number are optimized to achieve the desired linearity and reduce power consumption as well. Simulation results show that the A/D converter using 1.5bit per stage MDAC with switched capacitors and dynamic comparators efficiently reduces the power consumption.

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