Design of a 2.5Gbps Serial Data Link CMOS Transceiver

2.5Gbps 시리얼 데이터 링크 CMOS 트랜시버의 설계

  • 이흥배 (삼성종합기술원 i-Networking Lab.) ;
  • 오운택 (고려대학교 전자공학과 ASIC Lab.) ;
  • 소병춘 (고려대학교 전자공학과 ASIC Lab.) ;
  • 황원석 (고려대학교 전자공학과 ASIC Lab.) ;
  • 김수원 (고려대학교 전자공학과 ASIC Lab.)
  • Published : 2003.07.01

Abstract

This paper describes a design for a 2.5Gb/s serial data link CMOS transceiver based on the InfiniBand$^{TM}$ specification. The transceiver chip integrates data serializer, line driver, Tx PLL, deserializer, clock recovery, and lock detector. The designed transceiver is fabricated in a 0.25 ${\mu}{\textrm}{m}$ CMOS mixed-signal, 1-poly, 5-metal process. The first version chip occupies a 3.0mm x 3.3mm area and consumes 450mW with 2.5V supply. In 2.5 Gbps, the output jitter of transmitter measured at the point over a 1.2m, 50Ω coaxial cable is 8.811ps(rms), 68ps(p-p). In the receiver, VCO jitter is 18.5ps(rms), 130ps(p-p), the recovered data are found equivalent to the transmitted data as expected. In the design for second version chip, the proposed clock and data recovery circuit using linear phase detector can reduce jitter in the VCO of PLL.L.

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