Proceedings of the IEEK Conference (대한전자공학회:학술대회논문집)
- 2003.07b
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- Pages.1161-1164
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- 2003
A Study on Directed Technology Mapping for FPGA
- Kim, Hyeon-Ho (Chungbuk Provincial Univ. of Science & Technology) ;
- Lee,Yong-Hui (Sinsung College) ;
- Yi, Jae-Young (Technical Univ. of Budapest) ;
- Woo, Kyong-Hwan (Woosong Technical College) ;
- Yi, Cheon-Hee (Chongju University)
- Published : 2003.07.01
Abstract
We have developed an optimization algorithm based formulation for performing efficient time driven simultaneous place and route for FPGAs. Field programmable gate array(FPGAs) provide of drastically reducing the turn-around time for digital ICs, with a relatively small degradation in performance. For a variety of application specific integrated circuit application, where time-to-market is most critical and the performance requirement do not mandate a custom or semicustom approach, FPGAs are an increasingly popular alternative. This has prompted a substantial amount of specialized synthesis and layout research focused on maximizing density, minimizing delay, and minimizing design time.
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