A Study on Optimal Clock Period Selection Algorithm for Low Power RTL Design

저전력 RTL 설계를 위한 최적 클럭 주기 선택 알고리듬에 관한 연구

We proposed a study on optimal clock period selection algorithm for low power RTL design. The proposed algorithm use the way of maintaining the throughput by reducing supply voltage after improve the system performance in order to minimize the power consumption. In this paper, it select the low power to use pipeline in the transformation of architecture. Also, the algorithm is important the clock period selection in order to maximize the resource sharing. however, it execute the optimal clock period selection algorithm.