Effect of rapid thermal annealing on interface trap density by using subthreshold slope technique in the FD SOI MOSFETs

완전 결핍 SOI MOSFET의 계면 트랩 밀도에 대한 급속 열처리 효과

  • Jihun Oh (Nano Electronic Devices Team Electronics and Telecommunications Research Institute) ;
  • Cho, Won-ju (Nano Electronic Devices Team Electronics and Telecommunications Research Institute) ;
  • Yang, Jong-Heon (Nano Electronic Devices Team Electronics and Telecommunications Research Institute) ;
  • Kiju Im (Nano Electronic Devices Team Electronics and Telecommunications Research Institute) ;
  • Baek, In-Bok (Nano Electronic Devices Team Electronics and Telecommunications Research Institute) ;
  • Ahn, Chang-Geun (Nano Electronic Devices Team Electronics and Telecommunications Research Institute) ;
  • Lee, Seongjae (Nano Electronic Devices Team Electronics and Telecommunications Research Institute)
  • Published : 2003.07.01

Abstract

In this presentation, we investigated the abnormal subthreshold slope of the FD SOI MOSFETs upon the rapid thermal annealing. Based on subthreshold technique and C-V measurement, we deduced that the hump of the subthreshold slope comes from the abnormal D$_{it}$ distribution after RTA. The local kink in the interface trap density distribution by RTA drastically degrades the subthreshold characteristics and mini hump can be eliminated by S-PGA.A.

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