반도체 EDS공정에서의 패턴인식기법을 이용한 불량 유형 자동 분류 방법 연구

Automatic classification of failure patterns in semiconductor EDS Test using pattern recognition

Yield enhancement in semiconductor fabrication is important. It is ideal to prevent all the failures. However, when a failure occurs, it is important to quickly specify the cause stage and take countermeasure. The automatic method of failure pattern extraction from fail bit map provides reduced time to analysis and facilitates yield enhancement. This paper describes the techniques to automatically classifies a failure pattern using a fail bit map, a new simple schema which facilitates the failure analysis.