Proceedings of the IEEK Conference (대한전자공학회:학술대회논문집)
- 2003.07a
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- Pages.378-381
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- 2003
Design and Implementation of 10Gigabit Ethernet Frame Multiplexer/Demultiplexer
10기가비트 이더넷 프레임 다중화/역다중화기 설계 및 구현
Abstract
This paper presents a design and implementation of 10gigabit ethernet frame multiplexer/demultiplexer. In this paper, we discuss gigabit and 10 gigabit ethernet standard interfaces(GMII/XGMII) and we propose multiple gigabit ethernet frame multiplexing/demultiplexing scheme to handle 10gigabit ethernet frame instead of using 10gigabit network processor. And then 10gigabit ethernet frame MUX/DMUX is designed, verified and implemented using FPGA.
Keywords