대한전기학회:학술대회논문집 (Proceedings of the KIEE Conference)

대한전기학회 (The Korean Institute of Electrical Engineers)
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2.5 Gb/s 클럭 및 데이터 복원 회로의 설계

Design of a 2.5 Gb/s Clock and Data Recovery Circuit

  • 이영미 (경북대학교 대학원 전자공학과) ;
  • 우동식 (경북대학교 대학원 전자공학과) ;
  • 이주상 (경북대학교 대학원 전자공학과) ;
  • 김강욱 (경북대학교 대학원 전자공학과) ;
  • 유상대 (경북대학교 전기전자컴퓨터학부)
  • Lee, Young-Mi (School of Electronical Engineering and Computer Science, Kyungpook National Univ.) ;
  • Woo, Dong-Sik (School of Electronical Engineering and Computer Science, Kyungpook National Univ.) ;
  • Lee, Ju-Sang (School of Electronical Engineering and Computer Science, Kyungpook National Univ.) ;
  • Kim, Kang-Wook (School of Electronical Engineering and Computer Science, Kyungpook National Univ.) ;
  • Yu, Sang-Dae (Kyungpook National Univ.)
  • 발행 : 2002.11.30
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초록

A design of clock and data recovery (CDR) circuit for the SONET OC-48 using a standard 0.18 ${\mu}m$ CMOS process has been performed. The phase detector and the charge pump must be able to operate at the 2.5 Gb/s input data speed and also accurately compare phase errors to reduce clock jitter. As a phase detector, the Hogge phase detector is selected but two transistors are added to improve the performance of the D-F/F. The charge pump was also designed to be placed indirectly input and output. A general ring oscillator topology is presented and simulated. It provides five-phase outputs and 220 MHz to 3.12 GHz tuning range.

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