Design and Implementation of a Fully Synthesizable Bluetooth Baseband Module Considering IP Reuse

In this paper, we describe the structure and the test results of a Bluetooth baseband module we have developed. The module has a distributed buffer, i.e. FIFO, for data stream. Bus interface of the module is designed on the basis of interface of microprocessor widely used and the external interface is designed to consider chips connected directly. Since the module performs as many hardware efficient tasks as possible, processing load of microprocessor is very small. It can also be controlled either by software or by hardware for flexibility. The fully synthesizable baseband module was fabricated in a $0.25\mu\textrm{m}$ CMOS technology occupying $2.79\times2.8{\textrm{mm}^2}$ area. And an FPGA implementation of this module is tested for file and bit-stream transfers between PCs.