Proceedings of the IEEK Conference (대한전자공학회:학술대회논문집)
- 2002.07b
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- Pages.1058-1061
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- 2002
Transistor Sizing Considering Slew Information to Reduce Glitch Power in CMOS Digital Circuit Design
- Lee, Hyungwoo (Department of Computer Science, Sogang University) ;
- Kim, Juho (Department of Computer Science, Sogang University)
- Published : 2002.07.01
Abstract
This paper presents the method of low power optimization considering the glitch reduction in CMOS circuits. Our algorithm utilizes the information of MOS size, the load capacitance of fan-out, and input slew to calculate the output waveform by using the linear signal model. Therefore, the accurate waveform of glitch can be obtained for estimation of power dissipation caused by glitches. Our algorithm is applied to ISCAS’85 benchmark circuits and experimental results show 23% glitch reduction and 11% total power reduction.
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