32 Bit RISC Core modeling using SystemC

  • 최홍미 (전남대학교 컴퓨터공학과) ;
  • 박성모 (전남대학교 컴퓨터공학과)
  • Published : 2002.06.01

Abstract

In this paper, we present a SystemC model of a 32-Bit RISC core wi)ich is based on the ARMTTDMI architecture. The RISC core model was first modeled in C for architecture verification and then refined down to a level that allows concurrent behavior lot hardware timing using the SystcmC class library. It was driven in timed functional level that uses handshake protocol. It was compiled using standard C++ compiler. The functional simulation result was verified by comparing the contents of memory, the result of execution with the result from the ARMulator of ADS(Arm Developer Suite).

Keywords