Proceedings of the IEEK Conference (대한전자공학회:학술대회논문집)
- 2002.06b
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- Pages.237-240
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- 2002
Technology of Ni Silicide for sub-100nm CMOS Device
100nm 이하의 CMOS소자를 위한 Ni Silicide Technology
Abstract
In this W, a NiSi technology suitable for sub-100nm CMOS sevice is proposed. It seems that capping layer has little effect on the sheet resistance and junction leakage current when there is no thermal treatment. However, there happened agglomeration and drastic increase of Junction leakage current without capping layer. In other word, capping layer especially TiN capping layer is highly effective in suppressing thermal effect. It is shown that the sheet resistance of 0.12
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