Proceedings of the IEEK Conference (대한전자공학회:학술대회논문집)
- 2002.06b
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- Pages.161-164
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- 2002
CMOS 기곤 노이즈 모델을 위한 Layout으로부터 1차원 substrate 저항 추출 방법 및 guard ring의 효과 고찰
Abstract
This paper presents an 1-D substrate resistance value expression and compares the measured wave-form data with the calculated 1-D resistance network model. The remaining part is devoted to the effectiveness of guard ring varying its width and number.
Keywords