An Implementation of Protocol Converter using DPRAM and Flow Control

DPRAM과 흐름 제어를 이용한 프로토콜 변환 장치의 구현

This paper rotates to tile FPGA that is reffered to as the UTOSPI. The design goal of the FPGA is to convert the UTOPIA-3 bus interface to the SPI-3 bus interface, so that the SAR chips on the ATM interface board can be interfaced to the packet processor through this FPGA. We Propose a new architecture that has two Dual Port RAMs and flow control signals. To buffer data, the UTOSPI has a Dual port RAM in the receive direction and the same size of that in the transmit direction. This design has been implemented, compiled, and tested using a Xilinx Virtex-I XCV-300E FPGA.