대한전기학회:학술대회논문집 (Proceedings of the KIEE Conference)
- 대한전기학회 2002년도 하계학술대회 논문집 C
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- Pages.1546-1548
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- 2002
러빙 처리된 표면의 적층 절연막을 가지는 Pentacene TFT의 전기적 특성
ELECTRICAL CHARACTERISTICS OF PENTACENE THIN FILM TRANSISTORS WITH STACKED AND SURFACE-TREATED GATE INSULATORS
- Kang, Chang-Heon (Dept. of Electrical and control Eng., Hongik Univ.) ;
- Lee, Jong-Hyuk (Dept. of Electrical and control Eng., Hongik Univ.) ;
- Park, Jae-Hoon (Dept. of Electrical and control Eng., Hongik Univ.) ;
- Choi, Jong-Sun (Dept. of Electrical and control Eng., Hongik Univ.)
- 발행 : 2002.07.10
초록
In this paper, the electrical characteristics of pentacene thin film transistors(TFTs) with stacked and surface-treated gate insulators have been investigated. The semiconductor layer of pentacene was thermally evaporated onto the stacked gate insulators. For the gate insulating materials. PVP(PolyvinylPhenol) and polystyrene were spin-coated with two different stacking orders, PVP-polystyrene and polystyrene-PVP. Rapid solvent evaporation during the spin-coating processes of these insulating layers produces non-equilibrium phase morphologies accompanied by surface undulations on gate insulator interfaces. This non-equilibrium phase morphology affects the growth mode of the subsequent pentacene layer. Therefore, in order to smoothen the gate dielectric surfaces, gate dielectric surfaces were rubbed laterally along the direction from the drain to the source TFTs with with stacked and surface-treated gate insulators have provided improved operational characteristics.
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