Proceedings of the International Microelectronics And Packaging Society Conference (한국마이크로전자및패키징학회:학술대회논문집)
- 2001.11a
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- Pages.119-123
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- 2001
A Novel Chip Scale Package Structure for High-Speed systems
고속시스템을 위한 새로운 단일칩 패키지 구조
Abstract
In this paper, a new structure and fabrication method for the wafer level package(WLP) is presented. A packaged VLSI chip is encapsulated by a parylene(which is a low k material) layer as a dielectric layer and is molded by SUB photo-epoxy with dielectric constant of 3.0 at 100 MHz. The electrical parameters (R, L, C) of package traces are extracted by using the Maxwell 3-D simulator. Based on HSPICE simulation results, the proposed wafer level package can operate for frequencies up to 20GHz.
Keywords