Proceedings of the KIEE Conference (대한전기학회:학술대회논문집)
- 2001.07c
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- Pages.1451-1453
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- 2001
An SOI LDMOS with Graded Gate and Recessed Source
경사진 게이트를 갖는 Recessed Source SOI LDMOS
- Kim, Chung-Hee (School of Electronics Engineering, Ajou University) ;
- Choi, Yearn-Ik (School of Electronics Engineering, Ajou University) ;
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Chung, Sang-Koo
(School of Electronics Engineering, Ajou University)
- Published : 2001.07.18
Abstract
An SOI(Silicon-On-Insulator) LD(Lateral Double-diffused)MOS with graded gate and recessed source is proposed. The proposed structure can increase the breakdown voltage by reducing the electric field crowding at the edge of gate. Simulation results by TSUPREM4 and MEDICI have shown that the breakdown voltage of proposed device was found to be 52 V while that of conventional device was 45 V. At the same breakdown voltage of 45 V, the on-resistance of the LDMOS with graded gate and recessed source was 14.4 % lower than that of conventional structure.
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