대한전자공학회:학술대회논문집 (Proceedings of the IEEK Conference)

대한전자공학회 (The Institute of Electronics and Information Engineers)
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Partial SOI 기판을 이용한 고속-고전압 Smart Power 소자설계 및 전기적 특성에 관한 연구

Design of a New Smart Power ICs based on the Partial SOI Technology for High Speed & High Voltage Applications

  • 최철 (서강대학교 전자공학과) ;
  • 구용서 (서경대학교 전자공학과) ;
  • 안철 (서강대학교 전자공학과)
  • Choi, Chul (Dept. of Electronic Eng. Sogang Univ.) ;
  • Koo, Yong-Seo (Dept, of Electronic Eng. Seokyeong Univ.) ;
  • An, Chul (Dept. of Electronic Eng. Sogang Univ.)
  • 발행 : 2000.11.01
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초록

A new Smart rower IC's based on the Partial SOI technology was designed for such applications as mobile communication systems, high-speed HDD systems etc. A new methodology of integrating a 0.8${\mu}{\textrm}{m}$ BiCMOS compatible Smart Power technology, high voltage bipolar device, high speed SAVEN bipolar device, LDD NMOSFET and a new LDMOSFET based on the Partial SOI technology is presented in this paper. The high voltage bipolar device has a breakdown voltage of 40V for the output stage of analog circuit. The optimized Partial SOI LDMOSFET has an off-state breakdown voltage of 75 V and a specific on- resistance of 0.249mΩ.$\textrm{cm}^2$ with the drift region length of 3.5${\mu}{\textrm}{m}$. The high-speed SAVEN bipolar device shows cut-off frequency of about 21㎓. The simulator DIOS and DESSIS has been used to get these results.

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